India's Semicon 2.0: lower fab subsidies, a bigger bet on design
· TexaHub · Regional Tech Ecosystems, Semiconductors, Geopolitics & Tech
Two weeks after notification and days before SEMICON India, the ₹1,27,500-crore scheme's rules show where New Delhi is shifting money, and where execution risk now sits.
From approval to rulebook
India's government notified the Semicon 2.0 scheme on 31 August, setting out how a ₹1,27,500-crore outlay will be spent and who can claim it [1]. The Union Cabinet had approved the programme on 15 July; the notification supplies the incentive structure and eligibility criteria that companies need before they can apply [1]. Nikkei Asia put the outlay at $13.4 billion [2].
The scheme covers fiscal support across six segments of the value chain, including chip design, capital equipment, fabs, and assembly, packaging and testing [3]. The notification frames the aim as building "resilient, trusted, and sovereign semiconductor technologies" for national strategic and critical infrastructure, with local development of IP cores, chips, systems-on-chip and modules [3]. IT Secretary S. Krishnan said: "The objective of the scheme is self reliance and fostering a globally competitive industry" [1].
The timing matters. SEMICON India 2026 opens on 17 September in New Delhi, where the government will present Semicon 2.0 to the global equipment, materials and chip companies it is trying to attract [4]. This report examines what changed between the first and second phases, what the early commentary says, and which risks the new design shifts rather than removes.
What phase one delivered
Semicon 1.0 launched in 2021 with a ₹76,000-crore outlay [5]. The government says 12 projects have been approved across six states with investment commitments exceeding ₹1.64 lakh crore, spanning silicon and compound semiconductor fabs, display fabrication and advanced packaging, and that three facilities have started commercial production [5]. The Hindu identified those three as Micron's ATMP plant, Kaynes Semicon and the CG Semi OSAT facility [1].
Output so far is concentrated in back-end work. An IANS report carried by The Economic Times noted that the projects now producing are mainly in assembly, testing and packaging rather than advanced wafer fabrication, and that the Tata Electronics partnership with Taiwan's Powerchip at Dholera in Gujarat is targeting first chip output in December [6]. DIGITIMES reported analysts' view that commercial viability at Dholera could begin around 75% to 80% yield, that full competitiveness may require 85% to 90%, and that reaching stable yields could take 24 to 30 months [7].
On talent, the government says the Chips to Startup programme has deployed electronic design automation tools at 320 academic institutions and trained more than 68,000 students, and that 211 chips had been taped out by April 2026 [5]. Fortune India reported that those chips came from 75 institutions, with seven fabricated at nodes down to 12 nanometres [4]. Figures for the engineering workforce are reported inconsistently: the government backgrounder describes 85,000 skilled semiconductor engineers as a target "within this decade" [5], while the IANS report quotes Minister Ashwini Vaishnaw as saying 85,000 have already been trained in four years and that India aims to develop 100,000 [6].
Where the money moves
The most visible change is the subsidy rate for fabs. Silicon wafer fabs will receive 40% of eligible capital expenditure, on a pari passu basis, compared with 50% in phase one [8]. Applicants must propose a 300-mm facility with at least 40,000 wafer starts per month, own or license production-grade process technology, invest at least ₹20,000 crore and have revenue of at least ₹7,500 crore in one of the three preceding financial years [8]. Compound semiconductor, display and other specialised fabs receive 35% [1], with much lower thresholds for compound, photonics, sensor and discrete fabs: ₹500 crore of investment, ₹200 crore of revenue and 500 wafer starts a month [8].
Packaging is graded by sophistication. Advanced packaging, including 2.5D and 3D, wafer-level chip-scale packaging and heterogeneous integration, gets 35% of eligible capex, while legacy packaging gets 25%; both require ₹1,000 crore of capex and ₹200 crore of revenue [8]. A new pillar for equipment and materials offers up to 30% capex support for specified segments, plus a production-linked incentive of 10%, 8%, 6%, 4% or 2% of domestically sourced bill of materials for five years from FY29, capped at 50% of eligible capex [8]. Advanced R&D and talent projects can receive up to 75% of project cost, including operating expenditure [8].
Design support is restructured. Eligible startups and MSMEs can obtain milestone-linked seed funding capped at 50% of project cost or ₹15 crore, whichever is lower, and companies that have raised venture or private equity can receive government equity co-investment [8]. Larger firms can take royalty financing, repaying 5% of net revenue from the product until 1.5 times the support has been recovered [8]. A deployment incentive pays 9% of net sales for five years on new chips, IP or SoCs launched after the scheme was announced [8]. The scheme opens for applications for an initial three years, with the India Semiconductor Mission as nodal agency [8].
Taken together, the rules lower the state's share of the most capital-intensive projects while widening the base of eligible activity. That is a reasonable response to fiscal limits, but it also raises the bar for any new silicon fab investor, who must now fund 60% of a very large project without the cushion phase one offered.
Early verdicts
Pranay Kotasthane of the Takshashila Institution, writing in the Hindustan Times on 9 September, called the scheme "a definite improvement over Semicon 1.0" [9]. He highlighted four shifts: design moving to the centre of the scheme, the India Semiconductor Mission taking over design from C-DAC, specified fiscal backing for research and talent, and capex support recalibrated into a band of mostly 30% to 40% from phase one's uniform 50% [9].
He argued the old design-linked incentive, which reimbursed up to half of spending capped at ₹15 crore, suited the industry poorly, noting that only 24 of a target of 100 firms received support [9]. He welcomed the removal of a numeric cap on foreign shareholding in favour of a control test, but said the replacement "still retains the uncertainty" [9]. He also warned that bureaucrats managing equity stakes "will be structurally biased toward caution", and that state co-ownership of IP in the strategic-chip category, where C-DAC selects firms and co-owns the results, makes such companies "nearly non-fundable by private investors" [9]. His largest concern was administrative load, since the mission now runs ten categories, equity management, royalty tracking and investment decisions [9].
Nikkei Asia, writing before the notification, framed the drive against expert warnings about latecomer risk and an annual chip-related import bill expected to reach $240 billion by 2035 [2]. The IANS report cited a NITI Aayog estimate that India imports 90% to 95% of its semiconductors and that domestic demand could exceed $200 billion by 2035 [6]; it also described central subsidies of up to 50%, a figure that matches phase one rather than the new fab rate [6] [8].
Private capital and investment signals
Private funding remains small relative to the public outlay. Data from Tracxn reported by BusinessLine show $1.4 billion in all-time equity funding across 281 funded companies, with $701 million of that raised since 2025 and $228 million so far in 2026 [10]. Electronic manufacturing services led with $313 million raised since 2025, and Bengaluru accounted for 40.1% of all equity funding to date [10].
Supplier commitments continued in the run-up to SEMICON India. Karnataka's industries minister M B Patil said Applied Materials will invest ₹3,600 crore in the state over ten years in R&D, equipment manufacturing and software for chip production, a project expected to create 1,000 jobs [11]. DIGITIMES has reported that states are adapting labour rules to court chipmakers, citing Gujarat's approval of 12-hour shifts at Micron's Sanand plant [7]. Nikkei Asia reported that Prime Minister Narendra Modi had laid the foundation stone for a 25 billion-rupee facility in Andhra Pradesh, the first in southern India approved under the programme [2].
The gap between government outlays measured in lakh crore and private equity measured in hundreds of millions of dollars is the clearest sign that the ecosystem still depends on state money and on a handful of large corporate and foreign investors.
What to watch at SEMICON India
The conference runs from 17 to 19 September under the theme "Silicon to Systems: Building the Ecosystem" [4]. Fortune India reported that more than 600 exhibitors and 300 international companies are expected, with participants including ASML, Applied Materials, Tata Electronics, Micron, Rapidus, Lam Research and Tokyo Electron [4]. Krishnan said the event comes against "the on-ground success" of three operating projects and the launch of Semicon 2.0 [4].
Three questions will indicate whether the new framework is gaining traction. First, whether any company signals interest in a new 300-mm silicon fab at the 40% rate, given the ₹20,000-crore minimum [8]. Second, whether the equipment and materials pillar draws announcements from global toolmakers beyond R&D centres. Third, how quickly the mission publishes the detailed guidelines that Kotasthane noted are still needed to judge how equity stakes will be managed [9].
Beyond the conference, Dholera's first output, targeted for December [6], will be the first real test of front-end manufacturing in India. Semicon 2.0 has spread public money across more of the value chain; whether that produces a deeper ecosystem or a thinner spread of subsidies will depend on execution by an agency whose remit has just grown considerably.
Sources
[1] Govt notifies ₹1,27,500-crore Semicon 2.0; spells out eligibility norms, sops for chip ecosystem — The Hindu, 31 Aug 2026
[2] India pushes semiconductor drive as experts warn of latecomer risks — Nikkei Asia, 27 Aug 2026
[3] Govt notifies ₹1.27 trillion Semicon 2.0 scheme to boost chip sector — Business Standard, 31 Aug 2026
[4] Semicon India 2026: India's chip-design push gathers pace, with 68,000 students trained and 211 chips taped out — Fortune India, 15 Sep 2026
[5] Silicon Dreams: SEMICON India 2026 and the Making of a Chip Powerhouse — Press Information Bureau, 15 Sep 2026
[6] How India's $13 billion plan aims to boost self-reliance in chip production — The Economic Times, 9 Sep 2026
[7] India roundup: India's chip push moves beyond fabs as yield, supply chains and new technology become the next test — DIGITIMES, 24 Aug 2026
[8] India semiconductor subsidy: Who can apply under Semicon 2.0? Investment, revenue and eligibility rules — CNBC-TV18, 31 Aug 2026
[9] Semicon 2.0 gets it right on the issues that matter — Hindustan Times, 9 Sep 2026
[10] India's semiconductor sector draws $1.4 bn funding, half of it since 2025 — BusinessLine, 13 Sep 2026
[11] Chip maker Applied Materials to invest Rs 3,600 crore: Karnataka minister — The Economic Times, 15 Sep 2026