Huawei's Tau Scaling Law: A Design Answer to a Lithography Problem
· TexaHub · Semiconductors, Geopolitics & Tech
Huawei says folding logic circuits and optimising for signal time can deliver 1.4nm-class density by 2031 without EUV. The claims are bold and largely unverified.
What Huawei announced
Huawei used the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai this week to present what it calls the Tau Scaling Law, which it positions as a successor to Moore's Law [1] [2]. The presentation was given by He Tingbo, president of Huawei's semiconductor business, which Tom's Hardware identifies as HiSilicon [1] [2].
The company's central claim is that progress should be measured by reductions in signal propagation delay and system execution time rather than by shrinking transistor geometry [1]. Huawei said it has designed and mass-produced 381 chips based on the principle over six years [1]. It said Kirin processors launching in autumn 2026 will be the first to use a circuit architecture called LogicFolding, and that by 2031 its high-end chips will reach transistor density equivalent to 1.4-nanometre process technology [1]. Tom's Hardware reported that the first LogicFolding Kirin parts are expected in the Mate 90 smartphone series [2].
He framed the effort as open to outside collaboration, saying that "No single company can independently find all the answers along the path of semiconductor evolution" [1].
How the approach is meant to work
According to Huawei, LogicFolding restructures circuit layouts to shorten critical signal paths and reduce resistive and capacitive loads, with optimisation applied at device, circuit, chip and system levels [1]. Tom's Hardware describes it as folding and stacking logic circuits into a dual-layer structure, and reports Huawei's claims of a 55% increase in transistor density and a 41% improvement in power efficiency [2]. Futurum characterised the 55% figure as a density gain at a fixed manufacturing node [3]. Futurum also described the stacking gains as roughly equivalent to three years of traditional scaling without a process-node advance [3].
The logic is explicit about the constraint it addresses. He told the symposium that "Geometric scaling needs the most advanced litho tooling, and is rapidly approaching physical boundaries" [4]. US export controls restrict China's access to advanced lithography tools, design software and high-bandwidth memory, and ASML, which makes the EUV systems that conventional 1.4nm manufacturing would need, remains barred from shipping its most capable equipment to China [5]. A method that extracts density and speed from layout and stacking rather than from finer patterning would, in principle, reduce Huawei's dependence on tools it cannot buy.
Tom's Hardware also reported that Huawei aims to extend the architecture to its Ascend AI processors and data centre clusters by 2030 [2]. That would move the claims from smartphone chips, where Huawei controls the whole product, to the AI accelerators at the centre of US export policy.
Claims versus evidence
Nothing presented so far has been independently verified. The Next Web noted that the 381-chip figure is, for now, Huawei's alone, with no third-party audit [5]. Light Reading observed that the claims came without third-party validation, cited energy consumption as another concern and noted that He acknowledged "many challenges remain" [4].
There is also a question of novelty. Stacking logic and shortening interconnect are areas the wider industry is already pursuing. Futurum noted that TSMC and Intel retain a commanding process-node lead at 14A and 18A and that their own hybrid bonding roadmaps are closing ground, and argued that beyond a certain density "the bottleneck shifts from computation to communication among chips, memory, and racks" [3]. The Next Web put the open question directly: whether the law is "a coherent design philosophy or a rebrand of well-established techniques" [5].
Not every observer was dismissive. Omdia analyst Lian Jye Su, quoted by SiliconANGLE, said "it's an alternative path forward, and a breakthrough Huawei managed to find while facing supply chain challenges" [6]. Reports also differ in their framing of the timeline: SiliconANGLE and Tom's Hardware both contrast Huawei's 2031 target with TSMC's aim to mass-produce 1.4nm chips by 2028 [2] [6]. Light Reading noted that, even on Huawei's own timeline, 1.4nm-equivalent performance in 2031 would leave it several years behind TSMC [4].
What it means for the sanctions contest
Markets took the claim seriously enough to move. Tom's Hardware reported that shares of SMIC, China's largest contract chipmaker, rose 7.6% after the announcement [2].
The timing also matters for the AI accelerator market. A week earlier, Nvidia chief executive Jensen Huang said his company has "really largely conceded" China's AI chip market to Huawei, which he described as "very, very strong", while Nvidia reported no China data centre revenue for the quarter [7]. A credible domestic route to higher-density logic would strengthen Huawei's position in a market that its main foreign rival has, by its own account, largely exited.
The strategic significance is less about whether Huawei reaches a specific density figure in 2031 and more about the direction it signals. Export controls were designed around the assumption that denying the most advanced lithography would cap Chinese logic performance. If design-level and packaging-level gains can partly substitute for node shrinks, the cap becomes softer, and policy attention may shift towards electronic design automation, advanced packaging equipment and memory, all of which are already restricted to varying degrees [5].
Futurum identified immature tooling and export restrictions on partnerships with Western vendors as the main obstacles to broader adoption, warning that the approach risks accelerating a bifurcation of global semiconductor infrastructure rather than bridging it [3]. The first concrete test is close: the Kirin chips due this autumn [1]. Until teardown analysis and independent benchmarks are available for those parts, the Tau Scaling Law is best read as a roadmap and a statement of intent rather than a demonstrated result.
Sources
[1] HUAWEI Introduces Tau Scaling Law for Future Chips — Huawei via PR Newswire, 27 May 2026
[2] Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — Tom's Hardware, 25 May 2026
[3] Does Huawei's Tau Scaling Law Challenge the Logic Leadership of Intel and TSMC? — Futurum, 26 May 2026
[4] Huawei touts chip design breakthrough as answer to US sanctions — Light Reading, 26 May 2026
[5] Huawei unveils 'Tau Scaling Law' as China's workaround for US chip sanctions — The Next Web, 25 May 2026
[6] China's Huawei unveils new sanctions-busting chip architecture that replaces Moore's Law — SiliconANGLE, 25 May 2026
[7] [News] NVIDIA Earnings Spotlight: $20B CPU Sales Target in 2026, China Concession to Huawei, and Reporting Overhaul — TrendForce, 21 May 2026