HBM and CoWoS: Where the AI Accelerator Supply Chain Binds in 2026

2026-10-01 · TexaHub · Semiconductors, Artificial Intelligence, Technology Trends, Geopolitics & Tech

Memory makers and TSMC all describe demand outrunning supply into 2027 and beyond, shifting pricing power and allocation risk onto buyers of AI hardware.

Two constraints, one accelerator

A modern AI accelerator is only as available as its two scarcest inputs: stacks of high-bandwidth memory (HBM) and the advanced packaging that joins those stacks to the compute die. On both fronts, the companies that control supply spent the third quarter of 2026 telling investors that demand still exceeds what they can build. TSMC chairman and CEO C.C. Wei told analysts on 16 July that "our packaging capacity is so tight that now it's limiting my customers' growth" [13]. SK hynix, the largest HBM supplier, described "a market environment where customer demand exceeds supply capabilities" in its second-quarter results [1], and Micron said on 30 September that it does "not have line of sight to when supply and demand will return to balance" in DRAM [6].

Demand for the finished systems is not in doubt. Nvidia reported second-quarter fiscal 2027 revenue of $96.2 billion, with data center revenue of $89.0 billion, and guided third-quarter revenue to $108.0 billion, plus or minus 2% [14]. The company also said its Vera Rubin platform is "ramping into full production" with racks running at partners including CoreWeave, Google Cloud, Microsoft Azure, Oracle Cloud Infrastructure and Nebius [14]. The analysis that follows treats the memory transition and the packaging build-out as the two inputs most likely to set the pace of such deployments.

The technical step is substantial. The JEDEC HBM4 standard, finalised in April 2025, specifies a 2048-bit interface, transfer speeds of up to 8 Gb/s and total bandwidth of 2 TB/s per stack, with configurations from 4-high to 16-high and a maximum capacity of 64 GB [11]. JEDEC also set a nominal package thickness of 775 micrometres for both 12-high and 16-high stacks, which TrendForce said reduced the immediate pressure to adopt hybrid bonding [11]. A wider interface and taller stacks mean more silicon per accelerator, which is the starting point for why HBM consumes so much DRAM capacity.

The three HBM suppliers in mid-2026

SK hynix reported second-quarter 2026 revenue of 79.3187 trillion won and operating profit of 60.5426 trillion won, an operating margin of 76% [1]. It said it began mass shipments of HBM4 in the second quarter and plans to ramp production in the second half, and that it completed HBM4E sample shipments in the first half [1]. On its earnings call, management said HBM4 yields were "nearing the levels of HBM3E, which is already in the maturity stage", that HBM4E volume production is targeted for 2027, and that the company had "concluded LTA negotiations with around 10 customers" [2]. It also said 2026 capital expenditure is expected to reach "the high KRW 40 trillion range" and that it would pull forward mass production at its M15X fab [2]; the company separately said the cleanroom for phase one of its Yongin site is planned to open in early 2027 [1].

Samsung Electronics reported second-quarter consolidated revenue of KRW 171.5 trillion and operating profit of KRW 89.5 trillion, with its Device Solutions division posting KRW 89.2 trillion of operating profit [3]. The company said its memory business addressed AI demand "despite limited capacity", scaled up HBM4 sales and shipped what it called the industry's first HBM4E samples to major customers [3]. On the call, Samsung said it expects HBM4 sales to rise more than three-fold quarter-over-quarter in the third quarter and HBM4 to account for "well over 60%" of its HBM revenue mix in the second half [4]. CFO Soon-Chul Park said supply constraints are expected to be "even more severe in 2027 than 2026" and that the shortage will persist through 2028, in Samsung's view [4].

Micron reported fiscal fourth-quarter 2026 revenue of $54.23 billion and full-year revenue of $133.19 billion [5]. It said HBM revenue grew faster than total company revenue in the quarter, that it continues "to execute well on our ramp of HBM4", and that it is working with Nvidia on a custom HBM4E implementation, NV-HBM, for next-generation GPUs and NVLink Fusion platforms [6] [7]. On the call, Micron President and Chief Technology and Product Officer Scott DeBoer described NV-HBM as "the first major custom HBM product out in the market" [7]. Micron also said cleanroom preparation at its HBM advanced packaging facility in Singapore is ahead of plan, with initial output expected in early calendar 2027 [6].

Market share shifted noticeably during the HBM4 transition. Counterpoint Research data reported by Korea JoongAng Daily put SK hynix's share of HBM revenue at 50% in the second quarter of 2026, down from 58% in the first, with Samsung rising from 21% to 33% and Micron easing from 21% to 18% [8]. Counterpoint forecast that Samsung's share would increase further as it ramps HBM4 shipments [8]. These are revenue-based estimates from one research firm for a single quarter; they should not be read as a settled ranking, especially while each supplier's HBM4 volumes are still ramping.

Why HBM tightens the whole DRAM market

HBM's claim on DRAM output is larger than its share of bits suggests. TrendForce estimated that HBM will represent approximately 22% of major suppliers' total DRAM wafer input by the end of 2026 and 30% by the end of 2027, while its share of DRAM bit supply is approximately 9% and 13% over the same periods [9]. The research firm attributed demand growth to larger memory configurations, including AI ASICs moving from 96GB or 192GB to 216GB or 288GB per chip in 2026, and Nvidia's Rubin Ultra platform raising HBM capacity to 384GB per GPU [9]. The gap between those two shares suggests that each HBM bit consumes considerably more wafer capacity than a bit of conventional DRAM.

That trade-off links HBM pricing to commodity DRAM pricing. TrendForce said suppliers "are expected to adjust production allocation between HBM and conventional DRAM depending on HBM pricing outcomes" to keep profitability in line with conventional products [9]. In August, TrendForce, citing Korean outlet Bloter, reported that HBM profitability was estimated to trail DDR5 by roughly 40 percentage points after some DDR5 prices nearly quadrupled over the past year [10]. Micron's description of its own 2027 contracts fits this picture: it said it has completed agreements for "the vast majority" of its calendar 2027 HBM bit supply "with significant price increases year over year, narrowing the gross margin gap with conventional DRAM" [6].

Micron expects industry DRAM bit shipments to grow in the low-20s percentage range in both calendar 2027 and 2028, with the industry remaining supply-constrained in both years, and expects HBM bit shipments to grow faster than conventional DRAM through 2028 [6]. It said cleanroom additions, not only node transitions, are required to narrow the gap, and it plans to raise fiscal 2027 capital expenditure above prior plans, with a majority of the increase for construction aimed at cleanroom availability in late calendar 2028 and beyond [6]. The practical consequence is that new fab space announced in 2026 does little for HBM availability in 2027.

CoWoS: the packaging chokepoint

HBM stacks must be packaged next to a GPU or ASIC before they are useful, and TSMC's CoWoS is the dominant route for doing so. Asked about rival packaging technologies such as Intel's EMIB-T, Wei said TSMC would "welcome that additional flexibility in the market" because it would help TSMC's front-end wafer business, and he confirmed that "the majority is still CoWoS" of advanced packaging demand [13]. TSMC raised its full-year 2026 capital budget to between $60 billion and $64 billion [13].

TSMC did not give a CoWoS capacity growth figure on its July call [13], so outside estimates have to be used. TrendForce, citing Economic Daily News' account of institutional investor estimates, put TSMC's monthly CoWoS capacity in 2026 at 120,000 to 140,000 wafers, with OSAT partners adding another 50,000 to 60,000 wafers, so that total industry capacity could approach 200,000 wafers per month [12]. The same report said the CoWoS supply-demand gap was around 20% and could narrow to about 10% by the end of 2026 [12]. These are investor estimates rather than company disclosures and should be treated as indicative only.

Pricing and contracts: who carries the risk

Suppliers are using the shortage to move toward multi-year contracts. Micron said it has signed 26 strategic customer agreements, which it estimates at over 35% of its revenue through 2030, that some now extend into 2031, and that customer financial commitments under them have risen to $32 billion, the vast majority in cash deposits [6]. Samsung said it has finalised multi-year supply agreements with the top five global data center customers and is in final talks with five more [4]. SK hynix said it has long-term agreements with around 10 customers and that multi-year discussions continue because tight conditions are "expected to persist for a considerable period" [2].

Price expectations for 2027 vary, and the published figures come mostly from analysts and press reports rather than suppliers. In June, TrendForce said 2027 HBM contract talks had shifted toward HBM4, which it expects to become the mainstream generation, and headlined that contract prices could rise by multiples [9]. In August, TrendForce relayed analyst expectations, reported by Bloter, of HBM contract prices rising by more than 50% in 2027, and a UBS projection, cited in the same report, of 2027 HBM average selling prices rising by about 79% [10]. The same report cited Bloomberg as saying Nvidia plans to raise prices for Vera Rubin and Grace Blackwell servers by more than 15% in early 2027 [10]. None of these figures has been confirmed by the companies involved, and the spread between them shows how uncertain the outlook is.

Buyers already face the results on supplier income statements. Micron guided fiscal first-quarter 2027 revenue to $61.5 billion, plus or minus $1.5 billion [5], and Nvidia reported a 75.0% gross margin for its second fiscal quarter with third-quarter guidance of 74.0%, plus or minus 50 basis points [14]. This suggests that, so far, accelerator vendors have been able to absorb or pass on higher memory costs without a large margin squeeze, which in turn implies the cost is moving downstream to cloud providers and enterprise buyers.

What this means for AI hardware buyers

Several practical points follow from the evidence. First, allocation matters more than list price: with Micron reporting most of its 2027 HBM bits already contracted [6] and Samsung and SK hynix both signing multi-year agreements with their largest customers [4] [2], buyers without direct supplier relationships are likely to depend on what accelerator vendors and cloud providers choose to pass along. Second, the timing of HBM4 matters. Suppliers describe HBM4 ramping through the second half of 2026 [1] [4], so delivery schedules for HBM4-based systems are exposed to yield and qualification progress at each memory maker.

Third, the geopolitical layer has not loosened for HBM. US export controls announced in December 2024 placed new restrictions on high-bandwidth memory, covering US-origin HBM and foreign-produced HBM subject to US rules under the advanced computing foreign direct product rule [15]. Evidence on how far Chinese DRAM makers have progressed toward an alternative domestic HBM supply is thin in primary sources, and this report does not attempt to quantify it. Micron's pitch of "geographically diversified supply, including DRAM made in the U.S." [6] shows that supply location is now part of how memory is sold.

Finally, the timelines suppliers give point to relief arriving slowly. Micron's new cleanroom space is aimed at late calendar 2028 and beyond [6], Samsung's CFO expects the shortage to persist through 2028 [4], and the CoWoS supply-demand gap is estimated to narrow rather than close by the end of 2026 [12]. Our reading is that buyers planning 2027 deployments should treat memory and packaging availability, not accelerator roadmaps, as the main constraint on schedules, and should expect contract terms such as prepayments and multi-year commitments to become standard parts of the negotiation.